1. Field of the Invention
The present invention relates to a spread spectrum clock generator. In addition, the present invention relates to a circuit including an integrated circuit including the spread spectrum clock generator. Further, the present invention relates to an image reading device and an image forming apparatus, which use the spread spectrum clock generator. Furthermore, the present invention relates to a spread spectrum clock generating method.
2. Discussion of the Background
Recently, there is a need for an image forming apparatus such as digital copiers, which can produce high quality images at a high speed. Therefore, a need exists for an image reading device (scanner), which can read images at a high dot density and a high speed, so that the scanner can be used for such an image forming apparatus. In attempting to fulfill such a need, the scanning density and reading speed of recent scanners increases more and more. With increase in scanning density and reading speed of scanners, an electromagnetic interference problem is caused. In attempting to prevent occurrence of the problem, spread spectrum clock generators (hereinafter referred to as SSCG) have been used recently.
As illustrated in FIG. 12, which illustrates change of frequency of a clock signal with time relative to the reference frequency, a SSCG has a function of periodically modulating the frequency of an input clock signal. In addition, as illustrated in FIG. 13, which illustrates change of noise when plotting frequency and electric field strength on the horizontal and vertical axes, respectively, it becomes possible to decrease the peak level of emission noise (S1 and S2) from S1P to S2P per a unit time before or after the spread spectrum due to the spread spectrum effect.
SSCGs which constitute a phase locked loop (PLL) and input modulated signals (mod_sig) to a voltage controlled oscillator (VCO) of the PLL to generate a spread spectrum clock signal (ss_ck) as illustrated in FIG. 14 are well known as conventional SSCGs. In this regard, the voltage controlled oscillator (VCO) is an oscillator generating a clock signal having a frequency depending on the input voltage, wherein the voltage-frequency characteristic (i.e., V-f characteristic) thereof is linear. In addition, the VCO sensitivity (i.e., VCO gain) is defined as change of frequency (ΔF) caused when the voltage is changed in an amount of ΔV.
Since the VCO gain also varies depending on the semiconductor manufacturing process conditions, operation temperature, supply voltage, etc., it is difficult for the above-mentioned SSCGs to control the frequency modulation width with high precision. In addition, since the variation in modulation width is the variation in emission noise reduction effect, the EMI problem is caused depending on the property of the VCO itself and/or the use environment.
FIG. 14 is a block diagram illustrating a background SSCG. Referring to FIG. 14, a SSCG 1 is constituted of a phase comparator (PC) 2, a charge pump (CP) 3, a loop filter (LF) 4, an adder 5, a voltage controlled oscillator (VCO) 6, a divider 7, and a modulation signal generator (MOD_GEN) 8.
The phase comparator (PC) 2 detects the phase difference between an input clock signal ref_sig and a feedback clock signal (fb_ck) and outputs a signal having a pulse width depending on the phase difference detected. The charge pump (CP) 3 supplies a charge/discharge current, which depends on the phase difference detected by the phase comparator 2, to the loop filter (LF) 4. The loop filter (LF) 4 converts the current supplied from the charge pump 3 to a DC voltage while removing high frequency components from the thus generated voltage. The voltage controlled oscillator (VCO) 6 generates a clock signal having a frequency depending on the DC voltage supplied from the loop filter 4. The output from the voltage controlled oscillator (VCO) 6 is fed back to the phase comparator (PC) 2, wherein controlling is performed such that the feedback clock signal (fb_ck) has the same frequency as that of the input clock signal (ref_ck).
In this regard, a modulation signal (mod_sig) for use in modulating frequency is generated in the modulation signal generator (MOD_GEN) 8. The thus generated modulation signal (mod_sig) is blended with the output from the loop filter (LF) 4 to be input to the voltage controlled oscillator (VCO) 6. The modulation signal (mod_sig) has such a temporal profile as illustrated in FIG. 12. By inputting the modulation signal (mod_sig) to the voltage controlled oscillator (VCO) 6, a modulated clock signal (hereinafter referred to as spread spectrum clock signal (ss_ck)) is generated. In FIG. 14, 1/N and 1/M denote dividers 9 and 7, respectively, which divide the input clock signal (ref_ck) and feedback signal (clock) (fb_ck), respectively, to generate a spread spectrum clock signal (ss_ck) having an arbitrary frequency represented by the following equation (1):ss—ck=ref—ck*(M/N)  (1)
FIG. 15 is a block diagram illustrating the configuration of the modulation signal generator (MOD_GEN) 8. Referring to FIG. 15, the modulation signal generator (MOD_GEN) 8 is constituted of a memory (ROM) 8-1 and a digital to analog converter (DAC) 8-2. This is called a direct digital synthesizer (DDS). The ROM 8-1 stores table data (digital code) (code) representing the modulation signal profile (one cycle of a triangular wave, in this case). By sequentially reading out the data at the predetermined cycle of the modulation frequency (mod_freq), followed by conversion to a voltage using the DAC 8-2, a modulation signal (mod_sig) is generated. In addition, as illustrated in FIG. 15, an attenuator (ATT) 8-3 is connected with the output side of the DAC 8-2 to control the attenuation level so that the modulation width becomes a targeted modulation width (mod_wid_tgt). Since the modulation width is determined depending on the amplitude of the modulation signal (mod_sig), by adjusting the amplitude using the attenuator (ATT) 8-3, a spread spectrum clock signal (ss_sig) having a targeted modulation width (mod_wid_tgt) can be generated. In this regard, the modulation generator (MOD_GEN) 8 may be constituted of a charge/discharge circuit using a current source and a capacitor instead of the above-mentioned direct digital synthesizer (DDS).
FIG. 16 illustrates the input-output characteristic, i.e., voltage-frequency characteristic, of the voltage controlled oscillator (VCO). As mentioned above, the voltage controlled oscillator (VCO) 6 is an oscillator generating a clock signal having a frequency depending on the input voltage, wherein frequency linearly varies with voltage. Specifically, as illustrated in FIG. 16, when a voltage (V) is input, a clock having a frequency (f) is generated. In this regard, when voltage varies in an amount of ΔV (V±ΔV), frequency varies in an amount of ±Δf(f±Δf). Namely, by inputting a triangular modulation signal whose voltage varies in a range of V±ΔV, to the voltage controlled oscillator (VCO) 6, a spread spectrum clock signal (ss_ck), whose frequency varies in a range of f±Δf (i.e., varies with time like a triangular wave), can be generated.
Since the voltage controlled oscillator (VCO) 6 is constituted of a transistor, a bias voltage is generally applied thereto to optimize the operating point of the transistor. Therefore, an offset region is present in each of the lower voltage side and the higher voltage side of the voltage in the voltage-frequency characteristic illustrated in FIG. 16, and in general, the voltage controlled oscillator (VCO) 6 is used in an effective variable range in which frequency linearly varies with voltage.
However, the voltage-frequency characteristic of the voltage controlled oscillator (VCO) 6 varies depending on variables such as the semiconductor manufacturing process conditions, operation temperature and supply voltage. Therefore, the VCO sensitivity (i.e., VCO gain), which is defined as the voltage-frequency ratio (=Δf/ΔV, i.e., slope of the voltage-frequency characteristic curve), is largely influenced by such variables as mentioned above. When the same voltage V±ΔV is applied, the average frequencies of the VCO1 and VCO2 are the same according to the PLL principle. However, as illustrated in FIG. 17, even when the same voltage V±ΔV is applied, the VCO gains of the VCO1 and VCO2 are different from each other, and therefore the modulation widths thereof are different from each other (i.e., Δf1‡Δf2). This means that the modulation width of the spread spectrum clock signal (ss_ck) obtained by a SSCG varies depending on the VCO gain, resulting in variation of the EMI reduction effect.
In attempting to address the problem, i.e., in attempting to control variation of VCO gain to enhance the modulation precision of the SSCG, a published unexamined Japanese patent application No. (hereinafter referred to as JP-A) 2007-295027 proposes a technique in that a PLL generating an unmodulated clock signal (PLL clock signal) and a synchronous control circuit generating a spread spectrum clock signal while synchronizing the spread spectrum clock signal with the PLL clock signal are provided to control variation of VCO gain.
When the average frequency and the modulation width are varied by the same cause and the amounts of the variations are the same, the variations can be reduced. However, when the average frequency and the modulation width are independently varied, the variation of the modulation width cannot be reduced although only the variation of the average frequency can be reduced. In this regard, if the modulation width is varied in the direction opposite to that of the average frequency, the variation of the modulation width is further worsened.
JP-A2008-022345 discloses a SSCG, which includes a divider configured to output a divided output signal; a phase comparator configured to detect the difference between the divided output signal and the reference clock signal received; a charge pump configured to generate a charge/discharge signal depending on the phase difference; a loop filter configured to generate a differential signal depending on the charge/discharge signal; a modulation circuit configured to generate a modulated wave when the differential signal and a modulating wave are input thereto; and a clock generator configured to generate a clock signal having a frequency depending on the modulated wave. The SSCG further includes a modulating wave generating circuit configured to generate a modulating wave according to the clock signal.
In this SSCG, the modulating wave generating circuit generates according to the clock signal and the modulating wave is added to the signal output from the loop filter to generate a spread spectrum clock signal. Therefore, variation of the modulating wave caused by variables such as variations of the matching process, power source and environmental temperature can be reduced. The present inventor considers that it is necessary for the SSCG to control the frequency modulation width with higher precision.